STM32F103VET6 Alternatives: Two Graded Candidates at 100 Pins

An exact-PN lookup on STM32F103VET6 returns two campaign-safe candidates: GigaDevice GD32F103VET6, graded P2P, and Artery AT32F403AVET7, graded PIN. Both are LQFP100 parts with 512 KB of flash, and neither is a validated drop-in replacement. The P2P record keeps a narrower peripheral set and an 85 °C ceiling; the PIN record buys a 240 MHz core, a second CAN, a second SDIO interface and far more SRAM — paid for with a firmware port. At 100 pins the choice is decided by flash behaviour, peripheral budget and package detail, not by the grade alone.

The target is ST's Mainstream Performance Cortex-M3 with 512 Kbytes of flash at 72 MHz, in the high-density family that the datasheet documents with LQFP100 14 × 14 mm packages, 3 ADCs and 13 communication interfaces (ST product page; STM32F103xE datasheet). The ST store lists the VET6 in LQFP100 14 × 14 × 1.4 mm over -40 to +85 °C (ST store listing). Everything below is what the live cross-reference records returned for that exact orderable part number — a research result, not a substitution approval.

What the exact-PN lookup returned

Read straight out of the live cross-reference table, filtered to campaign-safe results:

Two records, two grades, six disclosed differences. Both are backed by manufacturer-master data, and both carry targetPnVerified set to false — the database's way of saying the match ran against the part-number string. Confirming the suffix, package and temperature code against your own BOM line is still your step.

Why 100 pins changes the candidate list

Pin count is not a detail you can round off. Run the same lookup at three densities and the candidate set changes each time:

The 48-pin and 64-pin results are published as STM32F103C8T6 alternatives and STM32F103RCT6 alternatives. Put the three side by side and a family-level query looks like a bad deal in both directions. The 100-pin exact lookup returns no AT32F413 at all, even though that family appears twice in the 64-pin result. And the 64-pin part has two Artery families to choose between, while the 100-pin part has one Artery candidate and one GigaDevice candidate.

A family search also cannot tell you that the 100-pin part is a 512 KB device in a 14 × 14 mm body. Pin count, flash density and package decide which records exist; the grade only describes the records that do.

The P2P candidate: GD32F103VET6

The live record lists LQFP100, 512 KB flash, 64 KB SRAM, up to 80 I/O, three 12-bit ADCs with 16 channels, two 12-bit DACs, five USARTs, three SPIs, two I2Ss, two I2Cs, one CAN 2.0B channel, USB 2.0, one SDIO interface and an EXMC external memory controller, at up to 108 MHz.

Each of the three disclosed differences is a real review item:

1. 108 MHz maximum versus 72 MHz on the target. A faster core is not automatically free: PLL and prescaler settings, cycle-counted delays and bus timing all need re-checking.
2. Zero-wait, SRAM-buffered flash. The record warns that the flash behaviour differs from ST's and that timing-sensitive code needs review against the target.
3. 1.2 V core supplied by an internal LDO, with ADC behaviour that differs. The record's instruction is to validate in-circuit, which is the only place ADC accuracy can be settled.

P2P says the manufacturer documentation supports a pin-to-pin mapping. It does not say the firmware is unchanged, and this record's own difference list is the proof.

The record's official-doc entry names a GigaDevice compatibility summary (V2.0) but attaches no URL; its second entry is a naming map matching ST's suffix convention. GigaDevice publishes the GD32F103xx datasheet as the document to read alongside it (GD32F103xx datasheet).

The PIN candidate: AT32F403AVET7

The record lists LQFP100 14 × 14 mm, 240 MHz, 512 KB total flash split into 256 KB zero-wait and 256 KB non-zero-wait, 96 + 128 KB SRAM, 80 GPIO, 16 12-bit ADC channels, two 12-bit DACs, four USARTs plus four UARTs, four SPI/I2S interfaces, three I2Cs, two CAN channels, one USB device interface, two SDIO interfaces and an XMC external memory controller, over -40 to +105 °C.

Its three disclosed differences:

1. 240 MHz versus 72 MHz. The record's instruction is to review peripheral clock configuration.
2. Firmware port required. Most registers are compatible but not all; an official migration guide and device pack are provided.
3. T7 temperature code. -40 to +105 °C, wider than the target's T6.

PIN therefore means the pin mapping is supported but the firmware port is part of the work. This record carries a URL-addressable archived manufacturer document, Artery migration guides, covering MG0007 (SXX32F103 to AT32F403A), MG0003 (to AT32F413) and MG0025 (to AT32A403A). That is a stronger evidence trail than the GD32 record's attached note, and it is worth saying so when the decision goes to a change-control board.

Same package, different resource budget

Both parts are 100-pin, 512 KB devices in the same body. The peripheral budget is where they stop resembling each other:

If the board uses one CAN, five USARTs and one SDIO interface, the GD32 record covers that budget and is the P2P grade. If it uses a second CAN, a second SDIO interface, more serial ports or larger buffers, the Artery part answers the resource question — after a port. Neither record says which one your firmware will accept. That is a design decision made with the datasheet open, and it is why two candidates in the same package can both be valid.

The GD32 record's sourcing strength is distributor; the Artery record's is data-only. That field describes the sourcing relationship behind the record. It is not a stock count, a lead time or a promise of supply.

The flash number that matters more than 512 KB

Both records say 512 KB. Neither means the same thing at execution time.

The GD32 record describes its flash as zero-wait and SRAM-buffered, and explicitly flags timing-sensitive code for review against ST. The Artery record splits its 512 KB into 256 KB zero-wait and 256 KB non-zero-wait. Two consequences follow for a real project: the linker script decides which routines sit in the fast region, and any cycle-counted loop, bit-banged interface or tight control ISR should be measured on the bench rather than inferred from the flash headline. A 512 KB match tells you the image fits. It does not tell you the timing holds.

The 100-pin checks a grade cannot cover

1. Package and land pattern. Both candidates are LQFP100, and the Artery record states 14 × 14 mm. Check body, pitch and courtyard against the existing footprint before ordering samples.
2. Power and ground distribution. A 100-pin part spreads supply pins differently from a 48- or 64-pin layout; verify decoupling and plane connections against the candidate pinout.
3. External memory interface. Both records list one (EXMC on the GD32, XMC on the Artery). If your board uses it, pin mapping and wait states belong in the datasheet diff, not in the grade. Follow how to read a migration guide.
4. ADC reference and channel map. The records describe the arrays differently: three 12-bit ADCs with 16 channels on the GD32 record, 16 12-bit channels on the Artery record. Check the reference pins and channel assignment against your schematic.
5. Interfaces that appear on only one side. A second CAN, a second SDIO interface and the extra USART/UART pair exist on the Artery record, not the GD32 one. If the board uses them, the shortlist is decided before clock speed is discussed.
6. Boot, debug and toolchain. Confirm the programmer, debug probe and device pack for the exact part, not for the family.
7. Temperature corner. The target and the GD32 record top out at 85 °C; the Artery part is rated to 105 °C. Test at the corner you actually ship to.
8. Bench validation. Run representative firmware on a sample and apply the receiving checks in incoming inspection and traceability.

What the records never contain

Price, MOQ, stock, lead time, delivery date and warranty are not part of a graded record, and nothing on this page should be read as one. The sourcing strength field describes the relationship behind the record — distributor for the GD32 part, data-only for the Artery part — and neither is a stock statement.

Both records are engineering-review candidates. The target-PN verification flag is false on both, which is a reminder that confirming your BOM line, suffix and package remains your step.

Senneon is an independent component supplier. Nothing in a cross-reference result implies affiliation with, authorization by, or endorsement from ST, GigaDevice, Artery or any other referenced manufacturer. Destination and end-use screening comes before any commercial commitment: restricted destinations and military or dual-use end uses are refused, and a line with an unclear end user is paused for human review rather than quoted.

For STM32F1 the underlying graded dataset is published under CC BY 4.0 at github.com/Woolis182/senneon-stm32f1-xref, so the records can be inspected directly.

Send one part number, not a family

Send one orderable PN or one BOM line and the answer comes back in the same shape as the tables above: candidates, grades, disclosed differences and the evidence attached to each one. That is a starting point for your design review, not a substitution approval; bench validation stays with your team. Send one part number for review, browse the cross-referenced catalog, or read how to submit a BOM for cross-check. If the question needs an engineer rather than a form, contact the desk.

— Senneon Engineering Desk. Last reviewed 2026-10-21.