STM32F103RCT6 Alternatives: Three Candidates, Two Artery Families, One Grade Boundary
A live exact-PN lookup on STM32F103RCT6 returns three campaign-safe candidates: GD32F103RCT6 graded P2P, plus two Artery parts graded PIN - AT32F403ARCT7 and AT32F413RCT7 - drawn from two different Artery families. Here is what each grade claims, the nine differences the records disclose, and why the exact pin count changes which candidates even appear.

An exact-PN lookup on STM32F103RCT6 returns exactly three campaign-safe candidates in the Senneon cross-reference database: GigaDevice GD32F103RCT6, graded P2P, and two Artery parts graded PIN - AT32F403ARCT7 and AT32F413RCT7. All three are high confidence, all three carry manufacturer evidence, and none is a validated drop-in replacement. Two of the three come from different Artery families, which is the part most single-target comparison pages leave out.
The target is a 64-pin, 256 KB part. ST lists the STM32F103RC as a Mainstream Performance line Arm Cortex-M3 with 256 Kbytes of flash running at 72 MHz, in an LQFP64 10x10 mm package over an operating range of -40 to +85 degC (ST product page; datasheet DS5792). Everything below is what the live records returned for that exact orderable part number - a research result, not a substitution approval.
What the exact-PN lookup returned
Read straight out of the live cross-reference table, filtered to campaign-safe results:
| Target PN | Candidate | Grade | Confidence | Evidence entries | Differences disclosed |
|---|---|---|---|---|---|
| STM32F103RCT6 | GD32F103RCT6 (GigaDevice) | P2P | high | official-doc + naming-map | 3 |
| STM32F103RCT6 | AT32F403ARCT7 (Artery) | PIN | high | official-doc (archived, linked) + naming-map | 3 |
| STM32F103RCT6 | AT32F413RCT7 (Artery) | PIN | high | official-doc (archived, linked) + naming-map | 3 |
Three records, two grades, nine disclosed differences. All three records also carry a target-PN verification flag that is currently false - a plain-language reminder that the lookup ran against the part-number string, and confirming the suffix and package against your own BOM line is still your step.
Why the exact PN decides which candidates appear
The published page for the 48-pin STM32F103C8T6 returns two candidates: GD32F103C8T6 at P2P and a single Artery part, AT32F413C8T7, at PIN. This 64-pin part returns three, and the third one is not a bigger version of the same silicon - it is a different Artery family entirely, AT32F403A.
That is the whole argument for exact-PN lookups over family lookups. STM32F103 is a family covering 36-pin through 100-pin parts with different flash densities, peripheral sets and packages. STM32F103RCT6 is one orderable part: 64 pins, LQFP, 256 KB flash, -40 to +85 degC. A family-level query hands you candidates for a part you may not be using, and it hides candidates that only exist at the density and pin count you actually need.
One P2P candidate - and the three differences it discloses
P2P means the manufacturer documentation supports a pin-to-pin mapping. It does not mean the part is interchangeable, and the same record that earns the grade publishes the reasons why. The three differences disclosed on the GD32F103RCT6 record, in the record's own words:
| Disclosed difference | Why it can move your design |
|---|---|
| Max clock 108 MHz vs 72 MHz | A faster core is usually welcome, but cycle-counted delay loops, bus timing and fixed peripheral clock ratios all need re-checking |
| Flash is zero-wait SRAM-buffered - timing-sensitive code needs review vs ST | Wait-state assumptions change; code that met timing on the target may behave differently |
| 1.2 V core via internal LDO; analog peripheral (ADC) behavior differs, validate in-circuit | ADC accuracy and reference behaviour are board-level facts, settled on the bench rather than in a table |
GigaDevice's own product selector lists GD32F103RCT6 as a Cortex-M3 in LQFP64 at 108 MHz with 256 KB flash, 48 KB SRAM, up to 51 I/O, 2.0B CAN and a 12-bit ADC (GigaDevice product selector) - the same headline flash density and pin count as the target, which is what makes a pin mapping possible at all. The difference list is what tells you the mapping is not the end of the work.
Two PIN candidates from two Artery families
Set the two Artery records beside each other and "PIN" stops being a single category:
| Field in the live record | AT32F403ARCT7 (PIN) | AT32F413RCT7 (PIN) |
|---|---|---|
| Series | AT32F403A | AT32F413 |
| Max CPU frequency | 240 MHz | 200 MHz |
| Internal flash | 256 KB (256 KB zero-wait) | 256 KB (96 KB zero-wait + 160 KB non-zero-wait) |
| SRAM | 96 + 128 KB | 32 / 64 / 16 KB (configurable) |
| Package | LQFP64 10x10 mm | LQFP64 10x10 mm |
| GPIO | 51 | 55 |
| 12-bit ADC channels | 16 | 10 |
| 12-bit DAC channels | 2 | not listed in this record |
| USART + UART | 4 + 4 | 3 + 2 |
| SPI / I2S | 4 / 4 | 2 / 2 |
| I2C | 3 | 2 |
| Operating temperature | -40 to +105 degC | -40 to +105 degC |
| Sourcing strength on the record | data-only | data-only |
Both are graded PIN, both are LQFP64, both are 256 KB flash - and they are not interchangeable with each other. The AT32F403A candidate carries roughly four times the SRAM and a wider peripheral set at 240 MHz; the AT32F413 candidate runs at 200 MHz with configurable SRAM and a different zero-wait split in its flash. Because SRAM size and zero-wait ratio are exactly the parameters firmware image size and cycle-critical loops depend on, choosing between these two is a firmware decision, not a sourcing one.
The PIN grade rests on the same disclosed difference in both records: "Firmware port required: most registers compatible but not all; official migration guide + device pack provided," alongside a max clock far above the target's 72 MHz and a wider -40 to +105 degC temperature grade. Pinout compatibility is the starting point; the register-level porting is the work.
The evidence is not equally strong in the three records
Look again at the evidence column. The records do not hand you the same kind of proof:
- Both Artery records carry an archived, URL-addressable manufacturer document: senneon.com/evidence/artery/mg-7c021cb7.pdf, covering the MG0007, MG0003 and MG0025 migration guides, each of which documents peripheral differences between an STM32F103 target and an AT32 family.
- The GigaDevice record's official-doc entry names its source - a GigaDevice compatibility summary between GD32 and STM32, V2.0 - but no URL is attached to that entry in the live record.
Both are legitimate starting points for a design review, and neither substitutes for reading the datasheet. They are not equally strong when you have to defend a choice in front of a change-control board, so ask which of the two you are being handed. Vendor migration documents are a real class of primary evidence; GigaDevice publishes them with a consistent structure covering pin compatibility, internal resources and program transplantation.
For the STM32F1 family the underlying graded dataset is published under CC BY 4.0 at github.com/Woolis182/senneon-stm32f1-xref, so you can inspect the records rather than take a page's word for them.
What the suffix tells you before the grade does
The target ends in RCT6 and all three candidates end in the same or a comparable code. In the ST naming the record's naming-map evidence tracks:
- R - 64 pins, which is why every candidate lands on LQFP64;
- C - 256 KB flash density, matched by all three candidates;
- T - the LQFP package family;
- 6 - -40 to +85 degC, versus T7 (-40 to +105 degC) on all three candidates.
The pin count and package align, which is what makes a P2P or PIN grade possible. The temperature grade differs on every candidate, and one character changes an entire operating envelope - a fact that shows up on a validation report, not in a headline. Reading the full orderable number first is the same discipline as keeping pin-compatible and drop-in compatible separate.
A qualification sequence for one 64-pin part
- Start from the full orderable PN, including pin-count, density, package and temperature code. A truncated number returns candidates for a different part.
- Read the grade, then the difference list. A grade without its differences is half a record.
- Check package, pin count and flash density against your actual footprint and firmware image size before anything else.
- Read every candidate's record in full when more than one exists - with two Artery PIN parts here, the higher grade does not tell you which one fits.
- Diff the datasheets on the parameters your design stresses - clock configuration, ADC behaviour, SRAM budget, zero-wait flash and temperature range - following how to read a migration guide.
- Bench-test a sample at the corner of the operating range you actually use, with the incoming inspection and traceability checks your process requires.
- File the engineering record and the commercial record separately, as covered in how procurement should document an approved second source.
What a graded cross-reference never contains
A graded record does not carry a price, a stock quantity, an MOQ, a lead time or a delivery date. The sourcing strength field on each record - data-only for the Artery candidates - describes the sourcing relationship behind the record; it is not a stock statement and not a lead time. None of the three records certifies that a part is in production today, and none carries a warranty term. Those are quotation and order facts, established per part number and per quantity.
Senneon is an independent component supplier. Nothing in a cross-reference result implies affiliation with, authorization by, or endorsement from ST, GigaDevice, Artery or any other referenced manufacturer. Destination and end-use screening applies before any commercial commitment: restricted destinations and military or dual-use end uses are refused outright, and a line with an unclear end user is paused for human review rather than quoted.
Put one exact part number through it
Send one orderable PN or one BOM line and you get back the graded candidates, the evidence type behind each one and the differences disclosed so far - the same shape as the tables on this page. That is a starting point for your design review, not a substitution approval; the bench validation stays with your team. You can browse the MCU records in the catalog, send one part number for review, or start a whole board with a BOM cross-check. If a question needs an engineer rather than a form, contact the desk.
Frequently asked questions
Can I replace STM32F103RCT6 with GD32F103RCT6 without changing code?
The live cross-reference record grades STM32F103RCT6 to GD32F103RCT6 as P2P at high confidence, which means the manufacturer documentation supports a pin-to-pin mapping - not that existing firmware runs unchanged. The same record discloses three differences: maximum clock 108 MHz versus 72 MHz, a zero-wait SRAM-buffered flash with different timing behaviour, and a 1.2 V core supplied through an internal LDO with differing analog (ADC) behaviour. Each needs validation on your board before production.
Why does STM32F103RCT6 have three candidates when the 48-pin STM32F103C8T6 has two?
The candidate pool depends on the exact orderable part number, not the family. A live lookup on the 64-pin, 256 KB STM32F103RCT6 returns GD32F103RCT6 at P2P plus two Artery PIN candidates from different families, AT32F403ARCT7 and AT32F413RCT7. The 48-pin STM32F103C8T6 lookup returns GD32F103C8T6 at P2P and a single Artery candidate, AT32F413C8T7. Pin count, density and package decide which mappings exist, so a family-level query can hide the right part or surface the wrong one.